signal edge
上緣觸發指令PLS(Pulse)
Rising Edge
rising edge (or positive edge)
rising edge-triggered
負緣 falling edge
falling edge (or negative edge)
In the case of a pulse, which consists of two edges:
The leading edge (or front edge) is the first edge of the pulse.
The trailing edge (or back edge) is the second edge of the pulse.
使用Verilog自定義原語（user defined primitives）時，正緣、負緣分別以(01)、(10)表示，也可以用縮寫字母r、f表示。
三菱PLC PLS和PLF指令的使用简介
階梯圖Ladder Diagram (LD)
PLS(Pulse)：上升沿微分输出指令。 PLF：下降沿微分输出指令
Flip-flop)致能(enable)或允動(gate)預置(preset)與清除(clear)邊緣觸發(edge-triggered)
正緣觸發(positive edge-triggered)
負緣觸發(negative edge-triggered)三態邏輯
三態邏輯 tri-state logic 或Three-state logic）有CS（晶片選擇，chip select）和OE（輸出使能，output enable）
上拉電阻（英語：Pull-up resistors）下拉電阻（Pull-down resistor）
0 1 Z (high impedance
Kleene and Priest logics
F U T
Buffer amplifier
Logic level
Metastability
Three-valued logic
Four-valued logic
Nine-valued logic
Don't care
Single pole, centre off (SPCO)
Multiplexer
verilog Symbol Comments
0 Logic 0
1 Logic 1
x Unknown, can be either logic 0 or 1. Can be used as input/output or current state of sequential UDPs
? Logic 0, 1 or x. Cannot be output of any UDP
- No change, only allowed in output of a UDP
ab Change in value from a to b where a or b is either 0, 1, or x
* Same as ??, indicates any change in input value
r Same as 01 -> rising edge on input
f Same as 10 -> falling edge on input
p Potential positive edge on input; either 0->1, 0->x, or x->1
n Potential falling edge on input; either 1->0, x->0, 1->x
true false R rising edge F falling edge
Verilog user defined primitives r f
https://www.javatpoint.com/verilog-user-defined-primitives
leading edge trailing edge positive edge-triggered negative edge-triggered Flip-Flop Circuit
https://zh.wikipedia.org/wiki/Verilog
